With the PCI Express (PCIe) specifications The same thing always happens: we start talking about the new versions when the previous ones have not even been established on the market.
It occurs of course with the new PCIe 6.0 specification, which has just been completed without PCIe 5.0 devices being available on the mass market. It will take us at least two years to see this type of peripheral in the consumer market, but be careful because this new version gives a notable leap in quality compared to its predecessors.
Doubling the bandwidth is great, but doing it that way is even better
We are still in fact beginning to enjoy the advantages of the PCIe 4.0 standard that for example has made an appearance on new generation consoles and it is largely responsible for the excellent performance of its SSDs.
With PCIe 5.0 something similar will happen: bandwidths doubled And we have already begun to see drives like Samsung’s that reach 13,000 MB / s of transfer when an SSD with a conventional SATA connection like the one we use in many PCs is around 500 MB / s (and that is already fast).
The fact is that we still have the PCIe 4.0 standard settling down and the PCIe 5.0 wanting to follow the steps, but the body that is in charge of the development of this standard has been working for years on the new PCIe 6.0 which now has just been finalized in terms of specs.
The improvements essentially affect bandwidth, which doubles that achieved with PCIe 5.0 and reaches 128 GB / s in the case of using all 16 tracks to transfer data. That is a guarantee for the future that will make the SSD units and graphic cards that we connect to these slots in the future to take full advantage of this data flow.
That is very important, but so is the way in which these improvements have been made. As indicated in AnandTech, PCIe 6.0 could be considered as the third major version of this specification.
PCIe 4.0 and PCIe 5.0 were more conservative and continued to use 128/130-bit signaling with the NRZ (Non-Return-to-Zero) system, in PCIe 6.0 it makes use of a major change and Pulse-Amplitude Modulation 4 (PAM4) technique is applied, which as Intel (PDF) indicates “doubles the number of electrical states of each cell or, in this case, of the transmission.”
To this technology, which was already applied in high-performance communication standards such as 200G Ethernet, other improvements are added such as the FEC (Forward Error Correction) system which, as its name indicates, allows to avoid errors during transmission.
The last of the keys is FLow control unIT (FLIT), an encoding method that does not work on the physical layer like PAM4, but on the logical layer.
All this contributes to the new specification taking an important qualitative leap that suggests that future versions will be even more relevant. Still PCIe 6.0 is still backward compatible, and the question that remains to be asked, of course, is when we will be able to see devices that take advantage of that specification.
The truth is that we will have to arm ourselves with patience to see them. It is estimated that It will still take 12-18 months to see the first implementations on the server side — which is where new capabilities come first — and from there we’ll have to wait another year or two to start seeing end-user devices.
There would therefore be target 2024 or even 2025 like the year in which perhaps we begin to see how this type of specification reaches our PCs and laptops, for example.
Vía | AnandTech
More information | PCI-SIG